This invention pertains to square root operation devices for use in data processors.
In many of conventional square root operation devices, square rooting is executed by the Newton-Raphson method. The first process of finding the square root of a numeric value A is to find out 1/.sqroot.A, and the next process is to result by A so as to obtain .sqroot.A. In the Newton-Raphson method, 1/.sqroot.A is found by means of convergent which the number of iteration to be carried out until a convergent condition is reached becomes lower as the initial value of a reciprocal approaches a true value. In such high-speed square root operation devices as set forth in U.S. Pat. No. 499,801 and relevant Japanese Patent Pub. No. 25924, a target (i.e., 1/.sqroot.A) is reached after convergent calculation about three or four times.
Additionally, there is a known square root operation device different from the foregoing type, which utilizes a technique similar to a square root computation based on "calculation-on-paper". In such a technique, a square is partially found by means of iterative calculation in descending order by the same number of digits each time, wherein the radicand is an initial, or the 0th partial residue, the (i+1)th partial square root is the i-th partial residue and the first to i-th partial square root values, the multiplicand is obtained by adding the (i+1)th partial square root value to twice the first to partial square root values, the product is found by taking the (i+1)th partial residue as a multiplier, and the partial residue is determined by subtracting the product from the i-th partial square root value. An example of square root operation devices based on this technique is shown in the paper of P. Montuschi and L. Giminiera, "ON EFFICIENT IMPLEMENTATION OF HIGHER RADIX SQUARE ROOT ALGORITHMS," Proc. 9th IEEE Symposium on Computer pp, 154-161, September 1989.
However, in the foregoing square root operation device according to the Newton-Raphson method, the significand part of a floating-point number input operand is input in a multiplying circuit as a multiplicand and a multiplier. Therefore, when finding the square root of a double-precision floating-point number in an IEEE standard, a 53.times.53 multiplying circuit, which corresponds to the bit length of a significand part with an addition of a leading bit, is required. When multiplication instructions and square root operation instructions are not executed at the same time and even when the multiplying circuit for executing a multiplication instruction is used for the execution of a square root operation instruction, no difficulties However, in the case that there is no data interdependence between the multiplication instruction and the square root operation instruction, and that both the instructions are carried out at the same time, a problem that hardware materials increase greatly arises due to the provision of such a 53.times.53 bit multiplying circuit for square root operation.
In the square root operation device proposed by P. Montuschi et al, the number of bits obtained by a single iterating calculation is two. Furthermore, when finding out the square root of a double-precision floating-point number in an IEEE standard, it is necessary to execute iterative calculation twenty-eight times in order that a 55-bit root made up of 53 bits for a significand part 53 bit for a guard bit and one bit for a round bit. As a result, such a proposed square root operation device is not suitable for high-speed operations.
The present invention provides a square root operation device by means of which square roots are founded at although the same uses an operand length for fixed-point numbers and a multiplying circuit smaller than the bit length of a significand part for floating-point numbers, as the bit length of a multiplier.